Step 2. Visually Verify Designs Are Correct

Verum’s ASD technology uses formal, mathematical methods to verify that your models are complete, precise and correct, and your design is error-free, before a single line of code has been written.

ASD:Suite verification checks a wide range of model properties,such as deadlocks, livelocks, illegal behaviour or race conditions. For each of these properties ASD:Suite verification will try to find an instance in which, for example, a deadlock situation occurs. When ASD:Suite verification has exhaustively explored all your design’s execution paths without finding any problems you can safely conclude that your design is defect-free.


Prevents	Assures
Deadlocks	Determinism
Livelocks	Guard completeness
Race conditions	Queue optimisation
Illegal behaviour	True invariants
State variable out-of-range errors	Implementation matches specification

Customer quotes

“ASD provides a framework that helps you model and design more thoroughly. It forces you to think about the requirements and cover all the exception cases.”

Ruud Derwig, Technology Manager at NXP

Step 2. Visually Verify Designs Are Correct

ASD:Suite

See it

Try it

Customer quotes

Product